The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 micron and under, such as 0.18 micron, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 micron and under generates numerous problems challenging the limitations of conventional interconnection technology, including conventional photolithographic, etching, and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric interlayer on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric material, such as spin on glass (SOG), is typically deposited to fill in the gaps between the metal features, and baked at a temperature of about 300.degree. C. to about 450.degree. C., for a period of time up to about two hours, depending upon the particular SOG material employed. Planarization, as by chemical-mechanical processing (CMP), is then performed.
The drive to achieve increased density and attendant shrinkage in feature size generates numerous problems. For example, as feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.25 micron and below, such as 0.18 micron, it becomes increasingly difficult to satisfactorily fill in the interwiring spacings voidlessly with a dielectric material and obtain adequate step coverage. It also becomes increasingly difficult to form a reliable interconnection structure. A through-hole is typically formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a landing pad occupying the entire bottom of the through-hole. Upon filling the through-hole with conductive material, such as a metal plug to form a conductive via, the entire bottom surface of the conductive via is in direct contact with the metal feature.
Another problem generated by miniaturization relates to the RC time constant. Although semiconductor devices are being scaled in the horizontal dimension, they are not generally scaled in the vertical dimension, since scaling in both dimensions would lead to a higher current density that could exceed reliability limits. Horizontal scaling, therefore, requires conductive lines having a high aspect ratio, i.e., conductor height to conductor width of greater than one, e.g., three or four with reduced interwiring spacings. As a result, capacitive coupling between conductive lines becomes a primary limitation on circuit speed. If intrametal capacitance is high, electrical inefficiencies and inaccuracies increase. It is recognized that a reduction in capacitance within multi-level metallization systems will reduce the RC time constant between the conductive lines.
Hydrogen silsesquioxane (HSQ) offers many advantages for use in interconnect technology. HSQ is relatively carbon free, thereby rendering it unnecessary to etch back HSQ below the upper surface of the metal lines to avoid poisoned via problems. In addition, HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.15 micron employing conventional spin-on equipment. HSQ undergoes a melting phase at approximately 200.degree. C.; it does not convert to the high dielectric constant glass phase until reaching temperatures of about 400.degree. C. in intermetal applications. As--deposited HSQ is considered a relatively low dielectric constant material with a dielectric constant of about 2.8-3.2, vis-a-vis silicon dioxide grown by a thermal oxidation or chemical vapor deposition which has a dielectric constant of about 3.9-4.2. The mentioned dielectric constants are based on a scale wherein 1.0 represents the dielectric constant of air.
However, in attempting to apply HSQ to interconnect technology, particularly for gap filling, it was found that its dielectric constant became undesirably high as a result of subsequent processing. For example, a layer of HSQ was initially deposited on a patterned metal layer to fill in gaps between metal features. Subsequently, an oxide layer was deposited and planarized. Such an oxide layer included silicon dioxide derived from tetraethyl orthosilicate (TEOS) deposited by plasma enhanced chemical vapor deposition (PECVD) in an oxygen-containing atmosphere at about 400.degree. C. Another such oxide layer is silicon dioxide derived from silane deposited by PECVD in an N.sub.2 O-containing atmosphere, at about 400.degree. C. It was found that after such depositions of silicon dioxide by PECVD, the dielectric constant of the deposited HSQ layer undesirably increased from about 2.8-3.2 to as high as about 4.0. This rise in dielectric constant is believed to result from the oxidation of the top surface of the HSQ due to exposure to an oxygen-containing ambient at an elevated temperature. The undesirable increase in the dielectric constant of the HSQ layer adversely impacts the intrametal capacitance and, therefore, circuit speed.
Accordingly, there exists a need for methodology enabling the use of HSQ as a dielectric material in interconnect technology, particularly for gap filling a patterned metal layer with subsequent deposition of an oxide and planarization, without adversely increasing the dielectric constant of the HSQ layer.